In the manufacture of a semiconductor device, a required device is produced by repeating various processings such as a film forming processing or an etching processing on a semiconductor wafer (hereinafter, simply referred to as “wafer”). To meet a recent demand for high speed and high integration of the semiconductor device and miniaturization of a wiring pattern thereof, it is required to reduce resistance (improve conductivity) of a wiring and improve electromigration resistance thereof.
To meet such requirements, copper (Cu), which has higher conductivity (lower resistance) than aluminum (Al) or tungsten (W) and has high electromigration resistance, is used as a wiring material.
As a method for forming a Cu wiring, there is proposed a technique in which a barrier film made of, for example, tantalum metal (Ta), titanium (Ti), tantalum nitride (TaN) or titanium nitride (TiN) is formed on an entire surface of an interlayer insulating film, which is formed on a wafer and provided with a trench and a via, by plasma sputtering as a physical vapor deposition (PVD) method; a Cu seed film is formed on the barrier film by the plasma sputtering as well; and Cu is plated on the Cu seed film to fill the trench and the via completely; residues of the copper thin film and the barrier film on a surface of the wafer is removed by CMP (Chemical Mechanical Polishing) (see for example, Patent Document 1).
However, a design rule of the semiconductor device is getting more miniaturized, and Cu has poor wettability for the barrier film. Besides, the PVD essentially has a low step coverage. Thus, in the technique described in Patent Document 1, it is difficult to form the Cu seed layer within the trench and the via appropriately, and the Cu seed layer narrows an opening of the trench and the via. If the Cu plating is performed in this state to bury the Cu in the trench and the via, a void may be formed in the buried Cu film.
In this regard, for the purposes of improving burying property of a fine wiring, there is proposed a technique in which Cu is buried after forming a Ru film having high wettability for Cu on a barrier film made of Ta or TaN by CVD (Chemical Vapor Deposition) which essentially has a high step coverage (see, for example, Patent Document 2).
Furthermore, there is also proposed a technique of burying a Cu film by ionized PVD (Physical Vapor Deposition) (iPVD) after forming the Ru film by the CVD as described above (see, for example, Patent Document 3). By burying the Cu by the PVD, impurities can be reduced as compared to a case of performing the Cu plating. Thus, the Cu wiring may have lower resistance.
In addition, there is also proposed a technique in which a barrier film and a wetting target layer made of Ru or the like are formed, by CVD, on an entire surface of an interlayer insulating film provided with recesses such as a via and a trench; a Cu film is formed by PVD; and a semiconductor wafer is then heated to reflow Cu on a surface thereof so that the recesses are filled with Cu (see, for example, Patent Document 4).
These techniques may be also applicable to a case of burying a Cu alloy in a recess by using a Cu alloy film instead of the Cu film.
Patent Document 1: Japanese Patent Laid-open Publication No. 2006-148075
Patent Document 2: Japanese Patent Laid-open Publication No. 2010-021447
Patent Document 3: Japanese Patent Laid-open Publication No. 2012-169590
Patent Document 4: Japanese Patent Laid-open Publication No. 2009-105289